用BIST造句子，“BIST”造句

Application of BIST in SoC Based Embedded Microprocessor Core

Research on Low Power Deterministic BIST Based on Genetic Algorithm-Folding Counter

Research of I_(DDT) ATPG Algorithm Based on Ambiguous Delay Assignments and BIST Test Pattern Generator Design;

在分析全掃描內建自測試(BIST)過高測試功耗原因的基礎上，提出了一種選擇部分寄存器成為掃描單元的部分掃描算法來實現低功耗BIST。

Keywords: Low power testing, BIST.

BIST-Based Delay-Fault Testing in Dynamic Reconfiguration FPGAs

Board-level Interconnect Test and BIST Implementation in Boundary Scan Environment

Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed Build in self test (BIST) for IP core chip tests.

另外，本文還針對IP核投片測試提出一種掃描測試電路結構，能夠實現測試芯片的掃描測試和高速內建自測試(BIST)。

Study on Mixed-signal BIST Based on Pseudo-random Testing;

This work will be greatly conductive to further study and the realization of BIST software test idea.

The Research on Logic BIST of SOC;

Based on the analysis of excessive power dissipation off ull-scan BIST, we present partial scan algorithm which selects a portion of registers for scan cells to implement low power BIST.

One Example of High Performance Memory BIST Design;

為了減少測試向量的存儲需求，提出一種基於扭環計數器作為測試向量產生器的橫向和豎向測試數據壓縮的BIST方案。

The Study on Built-in Self-test (BIST) for Integrated Circuits Based-on Multiple Scan Chains;

實踐*,該測試框架有利於BIST軟件測試思想的進一步研究和實現。